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ANALOG & MIXED-SIGNAL IC ENGINEER

Miguel Descalzo Pérez

I design analog and mixed-signal circuits in a full-custom ASIC workflow, from schematic and layout through tape-out. I currently work with flexible and organic electronics technologies.

L'Hospitalet de Llobregat · Barcelona, Spain

Portrait of Miguel Descalzo Pérez
01About

I am an analog and mixed-signal IC engineer based in Barcelona, working at FlexiIC on innovative organic electronics. Previously, I spent two years at IMASENIC, designing CMOS image sensors and taking projects from specification to tape-out, including a wafer-scale image sensor and SWIR image sensor. My experience covers the full IC design flow, from system definition, schematic and Verilog-AMS design, and HSPICE simulation to layout, verification, and top-level integration, across 180 nm, 130 nm CMOS, and 600 nm organic processes. Earlier, I worked at ASML testing DUV photolithography systems. I hold a Master's degree in Microelectronics from the Universidad de Sevilla and a degree in Electronics and Telecommunication Engineering from the Universitat de Barcelona, and I work in Catalan, Spanish, and English.

3
Tape-outs shipped
600–130
nm process nodes used
2019
In analog IC design since
3
Working languages
02Experience
EXP·01 Jul 2026 – Present
Analog/Mixed-Signal IC Engineer
FlexiIC · Sant Cugat, Spain

Design of flexible analog and mixed-signal circuits for sensor acquisition platforms with biomedical and industrial applications, using a VLSI workflow. Responsible for system description, top-level integration, and circuit design in a 600 nm nMOS-only process.
As an experienced member of the team, I am also responsible for defining the system architecture and partitioning it into sub-circuits.

  • Project planning and scheduling for a small team of engineers
  • Coordination and collaboration with testing and fabrication teams
  • Definition of input and output signals
  • Top-level integration & verification
  • Analog/mixed-signal circuit design (e.g. pad library, current DAC)
STATUS — First tape-out in progress
EXP·02 Jul 2024 – Jul 2026
Analog/Mixed-Signal IC Engineer
IMASENIC · Barcelona, Spain

Design of analog and mixed-signal circuits for innovative image sensors in a VLSI workflow, using Synopsys Custom Compiler and Calibre. Top-level integration and verification of systems designed in 180 nm and 130 nm processes.

  • Planned and scheduled personal responsibilities
  • Defined project characteristics against the specification and, together with the team, identified and resolved problems at the circuit level
  • Schematic and Verilog-AMS circuit description, followed by layout implementation
  • Electrical simulation (HSPICE) and design verification (DRC, LVS, ERC, antenna rule check)
  • Post-layout simulation and top-level integration of image sensors
KEY RESULTS — Tape-out of a wafer-scale CMOS image sensor · Tape-out of a SWIR image sensor with on-system depth extraction · Design and implementation of an LVDS driver
EXP·03 Mar 2022 – Aug 2023
Test Engineer
ASML · Eindhoven, Netherlands

System performance and operational testing before shipment of Deep Ultraviolet (DUV) photolithography systems, verifying sub-systems against the specification and diagnosing issues.

  • In-depth testing of sub-systems: lenses, chucks, reticle carrying unit, wafer carrying unit, and more
  • Final verification of DUV systems before disassembly and shipment
  • Manual clean-room operations: part replacement, rebooting, loading reticles and wafers
KEY RESULT — Created and verified the tool wafers and reticles used to calibrate several DUV systems
EXP·04 Jan 2020 – Jun 2020
Electronics Engineer — Internship
VHIR (Vall d'Hebron Institut de Recerca) · Barcelona, Spain

Built a system to help automate a headache and migraine study, by exposing participants to visual and auditory stimuli within safe, well-characterized limits.

  • Planned how to generate the required stimuli and identified safe exposure thresholds
  • Ensured that those thresholds could not be reached by the designed system
  • Automated stimuli generation and response capture from the test participant
EXP·05 Apr 2019 – Jan 2020
Microelectronics Engineer
Physics UB — SIC Research Group · Barcelona, Spain

Undergraduate research in the Communication and Instrumentation Systems group, researching implementations for a 10-bit ADC on a 350 nm process, using Cadence.

  • Investigated architectures against the ADC requirements
  • Designed and simulated possible solutions
EXP·06 Sep 2018 – Apr 2019
Computer Technician
Biology UB · Barcelona, Spain

Supported the computer rooms of the Biology Faculty: IT support for students, professors, and researchers, and upkeep of software and hardware.

03Education
Master in Microelectronics: Design and Applications of Micro/Nanoscale Systems
Universidad de Sevilla — Faculty of Physics · 2023–2025
Relevant areas: high-frequency microelectronics, analog and digital circuits.
Electronics and Telecommunication Engineering Degree
Universitat de Barcelona — Faculty of Physics · 2016–2020
Relevant areas: microelectronics, high-frequency electronics, embedded systems, PCB design, firmware, and transducers.
04Skills

EDA & SIMULATION

Synopsys Custom Compiler, Cadence Virtuoso, Calibre, KLayout, HSPICE, Verilog-AMS, Verilog

INTEGRATION & VERIFICATION

DRC, LVS, ERC, antenna rule check, post-layout simulation, VLSI top-level assembly and checks

DOMAIN

CMOS image sensors, ADC design, LVDS drivers, analog and mixed-signal IC design, schematic and layout implementation in 350 nm / 180 nm / 130 nm CMOS processes and a 600 nm organic process

LANGUAGES

English, Catalan (native), Spanish (native)

05Contact

Reach out to discuss interesting circuits, organic microelectronics, or simply to connect.